1. Field of the Disclosure
The present disclosure relates to a pressure sensor, and more particularly to a piezoresistive pressure sensor that is formed using MEMS technology.
2. Description of the Related Art
In the related art, as a pressure sensor that is formed using MEMS (Micro Electro Mechanical System) technology, a piezoresistive pressure sensor that uses a piezo element of which the resistance value is changed according to the deformation of a diaphragm is known (for example, see Patent JP-A-61-267372 (Document 1) and JP-A-11-68118 (Patent Document 2).
The piezoresistive pressure sensor 100, for example, as illustrated in FIG. 5A, is configured by forming piezo elements 110 approximately in the centers of respective edges of a diaphragm 103. Further, as clearly illustrated in FIG. 5B, each piezo element 110 is formed in a meander shape in which three semiconductor resistive layers 120, 121, and 122 are installed side by side at intervals, and the respective semiconductor resistive layers 120, 121, and 122 are connected by semiconductor interconnection layers 125 and 126 having a lower resistance than that of the semiconductor resistive layers 120, 121, and 122. Further, at both ends of the piezo element 110 that is formed in a meander shape, low-resistance semiconductor interconnection layers 123 and 124 are connected.
With the miniaturization of the pressure sensor 100, the distance between the interconnection layers that constitute the pressure sensor has been shortened. Particularly, in the piezoresistive pressure sensor, in terms of the principle that the resistance value of a piezo element is changed according to the deformation of a diaphragm, it is required to miniaturize the entire size of the piezoresistive pressure sensor while the arrangement shape of a semiconductor layer is not changed but is similarly maintained. Due to this, if the size is reduced to miniaturize the interconnection, for example, if the corner size of 1 mm (the width of 12 μm of the semiconductor layer) is miniaturized to the corner size of 0.5 mm (the width of 9 μm of the semiconductor layer), the distance between the interconnection layers is remarkably shortened, for example, to be equal to or less than 4 μm. Accordingly, if a voltage is applied to the circuit, the electric field distribution becomes non-uniform, and thus an ESD (ElectroStatic Discharge) breakdown may easily occur in an area where the electric field distribution is heightened. In particular, the ESD breakdown may easily occur between one corner portion R2 of the low-resistance semiconductor interconnection layer 126 that connects the high-resistance semiconductor resistive layers 121 and 122 together and a corner portion R1 of the low-resistance semiconductor interconnection layer 123 that extends from the high-resistance semiconductor resistive layer 120, and between one corner portion R3 of the low-resistance semiconductor interconnection layer 125 that connects the high-resistance semiconductor resistive layers 120 and 121 together and a corner portion R4 of the low-resistance semiconductor interconnection layer 124 that extends from the high-resistance semiconductor resistive layer 122.